Partial II preparation

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When to take this partial

After courses 5 through 9 on the study path: Delays, GPIO, Comparisons, and Practice 1.

Real exam difficulty

Part	Typical content
I — Theory	MOVF REGISTRO,F vs zero (Z); C and Z; pipeline; machine cycle
II — Development	REG1 > REG2 subroutine; C/Z after SUBWF; 3 ms delay @ 20 MHz
III — Problems	Pump countdown; line-following robot

Reference: Second Partial — PIC18F4550 Microcontrollers.

Required before the exam

1. Delays
2. Comparisons
3. GPIO and buttons
4. Practice 1

Course topics: Delays, comparisons, and GPIO

Software delays, register comparisons, GPIO, buttons, and Practice 1.

Reference material: Clase Tema 4 y 5.pdf · Practica 1 Operacion matematia.pdf

1. Review these lessons

Complete each page and pass its interactive exam before taking this partial.

• retardos
• retardos/ciclos-maquina
• retardos/bucles
• retardos/calculo-y-aplicaciones
• comparaciones
• comparaciones/banderas-c-z
• comparaciones/igual-cero
• comparaciones/entre-registros
• gpio
• gpio/botones
• practicas/primer-led

2. Lab practices

• practicas/operaciones-matematicas · step-by-step tutorial

3. Take the partial exam below

Minimum 70% to pass. A CALETAS account is required to take this exam and save your result.

Interactive exam

Partial II — Delays and comparisons

Based on: Clase Tema 4 y 5.pdf

0 of 0 answered

MOVF REGISTRO,F to compare to zero mainly affects flag...

Z (not C) C (not Z) GIE RBIF

The machine cycle with a 20 MHz crystal is...

0.2 µs 1 µs 4 µs 20 µs

The formula Delay = CM × Σ CI belongs to...

Software delays ADC ISR Proteus only

After MOVF B,W and SUBWF A,W with A=5, B=3, Z equals...

0 1 Undefined Equal to TRIS

After A-B with A=2, B=7 (unsigned), C equals...

0 1 2 7

For REG1 > REG2 you must check C=1 and...

Z=0 Z=1 GIE=0 ADON=1

CALL and RETURN in a delay typically add...

2 cycles each 1 cycle each 0 cycles 10 cycles

In a local delay loop BRA is used because...

Relative jump to the loop (course convention) Uses less Flash than any instruction Does not use the PC Disables interrupts

TRISB = 0xFF configures port B as...

All inputs All outputs Analog only UART

PIC18 pipeline overlap means that...

Instructions may overlap execution stages Two crystals are mandatory TRIS clears itself There is no machine cycle

To write a stable output on a pin you preferably use...

LATx Only read PORTx EECON1 ADRESH

A 3 ms delay @ 20 MHz is calculated using...

CM=0.2 µs and Σ CI of nested loops (+ NOP if needed) Only MOVF STATUS CCP PWM EEPROM only

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