Basic architecture
The PIC18F4550 uses a Harvard-style architecture, where program memory and data memory are separated. This allows the microcontroller to fetch instructions and handle data through different spaces.
PIC18F4550 block diagram
Section titled “PIC18F4550 block diagram”The six registers of the general scheme are in Basic concepts. This figure is this chip only:
The numbers beside the lines are not addresses. They say how many bits that path carries.
| Number | Where it is | What it means |
|---|---|---|
| 8 | Data bus, W, and the ALU | One byte. A value from 0 to 255 travels there. That is why 8 shows up on almost every data path. |
| 16 | Instruction bus | Each PIC18 instruction is 16 bits wide. It leaves Flash and enters the IR. |
| 12 | Data address and FSR | The address of one data byte. Twelve bits name 4096 locations. FSR (the PIC’s data-address register) is 12 bits. |
| 4 | BSR, next to the bank | Selects the data-memory bank. Those 4 bits, plus the 8 bits that come inside the instruction, make the 12-bit address. |
| 21 | Table pointer | A 21-bit pointer to one byte of program memory. Table reads and table writes use it. |
| 20 | Next to the program counter | The PC reaches bit 20. It is written PC<20:0>: from bit 0 through bit 20 that is 21 bits. The 20 on the drawing is that highest bit, the same width the PC uses to point at Flash. |
Important elements
Section titled “Important elements”| Element | Function |
|---|---|
WREG | Working register. Many operations go through it. |
STATUS | Stores flags such as zero, carry, and negative. |
SFR | Special function registers used to control peripherals. |
GPR | General purpose registers used as variables. |
BSR | Selects the memory bank to access registers. |
PC | Program counter. Points to the next instruction. |
Class names (any microcontroller) and the PIC18 name:
| In class | On the PIC18 |
|---|---|
| Classic accumulator (after the ALU) | The PIC does not work that way: W sits before the ALU (WREG) |
| STATUS | STATUS — flags C, Z, DC, N, OV |
| General-purpose registers | GPR — data-memory bytes you use as variables |
| Data-address register | Instruction address f (direct) or FSR (indirect) |
| SP | STKPTR — top of the stack |
| IR | Internal opcode register. You do not write it in the .ASM |
| PC and stack | PC and the hardware stack (stores addresses, not data) |
The table is a quick reference. Below you will find detailed explanations with examples from real lab work. The generic register set is in Basic concepts — registers.
Each element in detail
Section titled “Each element in detail”WREG — working register
Section titled “WREG — working register”In the general scheme the accumulator sits under the ALU: the result lands there, and that same value can go back in as an operand. A PIC does not work that way. W sits before the ALU: it is an operand that enters together with another value. The result can return to a register or to W.
| Traditional microprocessor | PIC18 | |
|---|---|---|
| Where it sits | The accumulator is under the ALU | W (WREG) is before the ALU |
| What enters the ALU | A value from the registers and, through the loop, the accumulator itself | W and another register |
| Where the result lands | Always in the accumulator | In a register (,F) or in W (,W) |
It is still the 8-bit working register (one byte, 0 to 255 — see What 8-bit means).
Think of it as the processor’s temporary hand: pick up a value, operate on it, then place it in a register or variable.
MOVLW D'5' ; load 5 into WREGADDLW D'3' ; WREG = 5 + 3 → WREG is 8MOVWF counter ; copy WREG to GPR 'counter'Without WREG you could not use MOVLW, add numbers, or move data between registers with most PIC18 instructions.
STATUS — result flags
Section titled “STATUS — result flags”After many operations, the PIC stores flags in STATUS. Each flag is one bit: either 1 (set/active) or 0 (clear/inactive). On an exam you need to know what each value means, not just the name.
| Bit | Name | What it measures |
|---|---|---|
| 0 | C | Carry |
| 1 | DC | Digit carry (low nibble) |
| 2 | Z | Zero result |
| 4 | OV | Signed overflow |
| 7 | N | Result sign (bit 7) |
What active (= 1) vs inactive (= 0) means
Section titled “What active (= 1) vs inactive (= 0) means”| Flag | = 1 (active) | = 0 (inactive) |
|---|---|---|
| Z | The operation result is zero | The result is not zero |
| C | There was carry past bit 7 (in addition: value exceeds 255 in unsigned 8 bits) | No carry out of the byte |
| DC | There was carry in the low nibble (bit 3 → 4) | No digit carry |
| N | Bit 7 of the result is 1 → negative number in two’s complement (signed) | Bit 7 is 0 → not negative in signed 8 bits |
| OV | Signed overflow: result does not fit in -128 to +127 | Signed operation was valid |
Numeric example with Z — is counter zero? The PIC has no CMP (compare) instruction; you compare by operating and reading the Z flag in STATUS:
MOVLW D'0' ; WREG = 0 (what we compare against)XORWF counter, W ; XOR counter and WREG bit by bit → result in W ; (XOR gate: matching bits → 0, different bits → 1) ; counter unchanged; only W and flags update ; ; if counter = 0: every bit matches WREG ; → result 00000000 → Z = 1 (active) ; if counter = 5: some bits differ from zero ; → result 00000101 → Z = 0 (inactive)Example with C after addition. WREG holds only 8 bits (2⁸ = 256 values: 0 to 255); if the sum exceeds 255, what does not fit is recorded in C and W keeps the remainder:
MOVLW D'200' ; WREG = 200ADDLW D'100' ; 200 + 100 = 300 ; 300 > 255 → does not fit in 8 bits ; 256 overflows (one full byte) → C = 1 (carry) ; WREG holds: 300 - 256 = 44You use flags to make decisions with conditional branches:
MOVLW D'0' ; reference: compare against 0XORWF counter, W ; counter == WREG? → if equal, result 0, Z=1BTFSS STATUS, Z ; skip if Z=1 (counter was 0)GOTO continue ; if Z=0 → jump to destinationGOTO handle_zero ; if Z=1 → jump to destinationhandle_zero: ; counter was 0 ...continue: ; counter was not 0 ...BTFSC skips when the flag is 0; BTFSS skips when it is 1.
On an exam: “How do you know an operation gave zero?” → Z = 1. “How do you know an addition overflowed past 255?” → C = 1.
SFR — special function registers
Section titled “SFR — special function registers”SFRs (Special Function Registers) control internal hardware: ports, timers, ADC, UART, interrupts, and more. Each bit or byte has a fixed meaning defined by Microchip.
Real example — turn on an LED on RB0. To change one bit of an SFR without touching the others, the PIC uses BCF (Bit Clear File → sets the bit to 0) and BSF (Bit Set File → sets the bit to 1):
BCF TRISB, 0 ; TRISB is an SFR, bit 0 → force that bit to 0 ; (bits 1..7 of TRISB stay unchanged) ; on TRISB: 0 = output → RB0 becomes an outputBSF LATB, 0 ; LATB is an SFR, bit 0 → force that bit to 1 ; (bits 1..7 of LATB stay unchanged) ; RB0 goes high → LED onYou are not writing the whole byte: BCF/BSF only change the bit you specify; the rest of the register stays the same. TRISB and LATB are fixed hardware names — you do not invent them.
Other SFRs you will use soon: INTCON (interrupts), TMR0 (Timer0), ADCON0 (ADC).
GPR — general purpose registers
Section titled “GPR — general purpose registers”GPRs are RAM bytes your program uses as variables: counters, temporaries, state-machine states, and so on. They do not control hardware directly; they hold data.
With counter RES 1 you do two things at once: the name (counter) defines the variable — a symbol you will use in code — and RES 1 reserves 1 byte of RAM for it. Later when you write INCF counter, F, the assembler already knows which address that is.
; In the variable section:counter RES 1 ; define 'counter' and reserve 1 byte in RAM
; In code:INCF counter, F ; counter = counter + 1MOVF counter, W ; copy counter to WREGDECFSZ counter, F ; decrement; if zero, skip next instructionGOTO waitThe key difference from an SFR: counter is yours — you name it and use it however you need. TRISB is not — its name and function come from the hardware.
BSR — bank selector
Section titled “BSR — bank selector”Both SFRs and GPRs live in data RAM, split into banks (0 through 15). The BSR register tells the CPU which bank you are in when you access an address.
Many SFRs (TRISB, LATB, INTCON…) live in the access bank and do not require touching BSR. But if you place GPR variables in different banks with RES, you must select the correct bank:
; 'temp' declared with: temp RES 1MOVLW 0x01MOVWF BSR ; activate bank 1CLRF temp ; clear the GPR variable in that bankCLRF BSR ; return to bank 0PIC18 ALU and the d parameter
Section titled “PIC18 ALU and the d parameter”The ALU combines two operands and writes the result. On the PIC18 one operand is usually W (or a literal embedded in the instruction) and the other is a file register f (GPR or SFR). Flags go to STATUS.
The d (destination) bit says where the result goes:
d | In source | Where the result goes |
|---|---|---|
| 0 (destination 0) | ,W | Into accumulator W |
| 1 | ,F | Into register f |
ADDWF counter, W ; d = 0 → W = W + counter; counter unchangedADDWF counter, F ; d = 1 → counter = counter + WAddressing modes
Section titled “Addressing modes”How the instruction says where the data comes from:
| Mode | Meaning | Example |
|---|---|---|
| Literal | The number travels inside the instruction. It is not read from RAM. | MOVLW .5 |
| Direct (general) | The instruction names the register (f). That name is the data-memory address. | MOVF counter, W |
| Indirect | FSR is the data-address register. INDF is the byte at that address. | MOVF INDF, W reads what FSR points to |
More on literals and ,W / ,F in Assembly.
MOVLW .20MOVWF FSR0L ; data-address register = 0x20MOVF INDF0, W ; W = byte at that addressPC, stack, and jumps
Section titled “PC, stack, and jumps”PC (Program Counter) points to the next instruction in Flash. You do not write it by hand: GOTO, BRA, CALL, and RETURN change it.
The PIC18 stack is an array of PC addresses, not variables. It is LIFO. STKPTR (the SP) marks the top.
- PUSH: stores an address.
CALLPUSHes the return address, then loads the PC with the destination. - POP: removes that address and puts it in the PC.
RETURNperforms the POP.
CALL must return. Without RETURN (or RETFIE in an interrupt), that address never leaves the stack: the program does not resume where it was, and repeated CALLs without a return fill the stack.
An interrupt also PUSHes the PC. RETFIE POPs it and re-enables interrupts. See Interrupts.
| Instruction | What it does to the PC | Uses the stack? | When to use it |
|---|---|---|---|
CALL | Jumps to a subroutine | Yes — PUSH | Code that must return (RETURN) |
RETURN | Goes back to the stacked address | Yes — POP | End of a CALL |
GOTO | Jumps to any label | No | Long jumps or loops that are not subroutines |
BRA | Short relative jump | No | Local loops, such as a delay |
BRA and GOTO change the PC without saving a return address. That is why a delay loop uses BRA, not CALL. Cycle comparison in Delay calculation — BRA vs GOTO.
start: CALL delay ; PUSH PC; jump to delay GOTO start ; no stack: only changes the PC
delay: ; ... RETURN ; POP: PC returns just after the CALLMental execution cycle
Section titled “Mental execution cycle”- The PIC reads an instruction from program memory.
- It decodes it.
- It executes the operation.
- It updates registers, flags, or peripherals.
- It moves to the next instruction unless there is a jump or interrupt.
Exam-style question
Section titled “Exam-style question”Why is it important to distinguish SFR and GPR?
Because SFRs control internal hardware such as ports, timers, and interrupts; GPRs are working memory used as program variables.
Architecture and CPU elements
Based on: Clase Tema 2 y 3 (1).pdf
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